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B. Keeth, B. Johnson, J. Baker, F. Lin, DRAM Circuit Design, Fundamental and High-speed Topics, Piscataway, NJ: IEEE Press 2007 A modern, comprehensive introduction to DRAM for students and practicing chip designers Dynamic Random Access Memory (DRAM) technology has been one of the greatest driving forces in the advancement of solid-state technology. With its ability to produce high product volumes and low pricing, it forces solid-state memory manufacturers to work aggressively to cut costs while maintaining, if not increasing, their market share. As a result, the state of the art continues to advance owing to the tremendous pressure to get more memory chips from each silicon wafer, primarily through process scaling and clever design. From a team of engineers working in memory circuit design, DRAM Circuit Design gives students and practicing chip designers an easy-to-follow, yet thorough, introductory treatment of the subject. Focusing on the chip designer rather than the end user, this volume offers expanded, up-to-date coverage of DRAM circuit design by presenting both standard and high-speed implementations. Additionally, it explores a range of topics: the DRAM array, peripheral circuitry, global circuitry and considerations, voltage converters, synchronization in DRAMs, data path design, and power delivery. Additionally, this up-to-date and comprehensive book features topics in high-speed design and architecture and the ever-increasing speed requirements of memory circuits. |
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The bulk of my patent portfolio is focused on high speed timing control using delay-locked or phase-locked loops. Clock distribution, duty-cycle and latency control, and high-speed data path are the other areas of interest. Please see the list for over 70 issued US and/or foreign patents. [Selected Publications]
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