Lin's Adventure



University of Idaho, Boise, ID Ph.D. in Electrical Engineering, August 1997 – May 2000 Research & design in VLSI, phase-locked and delay-locked loops, memory interface, ADC, DAC, and clock distribution. Dissertation: “Research and Design of Low Jitter, Wide Lock Range, All-Digital Phase-Locked and Delay-Locked Loops” (PDF format) University of Electronic Science and Technology, 电子科技大学，Chengdu, China Master of Engineering in Electrical Engineering (EE), September 1992 – May 1995 Bachelor of Engineering in EE, September 1988 – July 1992 Chengdu No. 7 High School , 成都七中，Chengdu, China Technical training & Short course Micron DRAM Basic Travelers – 60 Series (50nm), January 2009, Boise, ID ISSCC 2007 Short Course, “Analog, Mixed-signal, and RF Circuit Design in Nanometer CMOS”, February 15, 2007, San Francisco, CA Mead Microelectronics, Inc. “Advanced Analog Design Techniques”, November 2005, San Diego, CA "Circuit Design for Digital Communications”, December 1998, Monterey, CA Introduction to Verilog-2001 Design, November 2004, Boise, ID

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