Micron Technology, Inc., Boise, ID
Senior Member of Technique Staff, 2007 – present
- Defined and developed various timing solutions for high-speed, high-performance memory products including GDDR5, DDR4 and 3-DI memory system using TSVs (through silicon vias)
- Involved and helped to shape strategic timing decisions and specifications for advanced memory products, including low power mobile, next generation main memory and emerging memories
- Solved highly complex timing problems by exploring various technologies and practically applying the technologies for memory products
- Led various mixed-signal circuit designs including phase-locked and delay-locked loops (PLL&DLL) with a clock frequency up to 2GHz for precise timing control and synchronization
- Consulted in several projects at different sites of the company
Designer, 2000 – 2007
- Developed various timing solutions for different memory products including DDR, DDR2/3 and graphics SDRAM (GDDR3/4)
- Designed high performance analog circuits like voltage reference (Bandgap), voltage regulator, current-mode logic, oscillator (VCO) and analog-to-digital converter (ADC) etc.
- Participated in high-speed I/O design including transceivers, clock distribution network, slew-rate control and programmable impedance control
- Promoted to Micron TCL (Technical Career Ladder) Fellow in 2005 and highly selective TLP (Technical Leadership Program) Senior Member of Technical Staff (SMTS) in 2007
Intern, summer 1998 & 1999
- Developed digital PLL and DLL for double-data-rate (DDR) DRAM
- Involved in high-speed sync-link DRAM design (SLDRAM)
AF Technology, Ltd., Zhuhai, China
System Engineer, July 1995 – May 1997
Mainly involved in developing and integrating a portable cardiac monitoring system
