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Patent issued (PDF) as of November 23, 2009 Phase-locked and delay-locked Loops, sychronous mirror delay and others | |
| Authors | Patent Title |
| R. J. Baker, F. Lin | "Digital dual-loop DLL design using coarse and fine loops" |
| F. Lin | “System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines” |
| F. Lin | “Interleaved delay line for phase locked and delay locked loops” |
| F. Lin, R. J. Baker | “Phase splitter using digital delay locked loops” |
| F. Lin | “Capture clock generator using master and slave delay locked loops” |
| F. Lin | “System and method to improve the efficiency of synchronous mirror delays and delay locked loops” |
| V. Mikhalev, F. Lin | “Method and apparatus for enabling a timing synchronization circuit” |
| F. Lin, T. Gomm | “Methods and apparatus for delay circuit” |
| F. Lin, B. Keeth | “Fast locking digital pahse locked loop” |
| F. Lin, B. Keeth, B. Johnson | “Method and system for delay control in synchronization circuits” |
| F. Lin, B. Johnson | “Method and apparatus for improving stability and lock time for synchronous circuits” |
| F. Lin | “Delay lock circuit having self-calibrating loop” |
| Feng Lin | “Centralizing the lock point of a synchronous circuit” |
| F. Lin | “Measure-controlled delay circuits with reduced phase error” |
| SH. Lee, F. Lin | “Phase-locked loop circuits with reduced lock time” |
| F. Lin | “Method and apparatus to set a tuning range for an analog delay” |
| F. Lin | “Delay-lock loop and method adapting itself to operate over a wide frequency range” |
| F. Lin | "Efficient clocking scheme for ultra high-speed systems" |
| F. Lin | "Loop filtering for fast PLL locking" |
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Duty-cycle correction & Phase detection | |
| Authors | Patent Title |
| F. Lin, R. J. Baker | “Phase detector for all-digital phase locked and delay locked loops” |
| B. Johnson, F. Lin | “Duty cycle distortion compensation for the data output of a memory device” |
| F. Lin | “Methods and apparatus for duty cycle control” |
| F. Lin | “Phase detector for reducing noise” |
| F. Lin | "Phase detector and method providing rapid locking of delay-locked loops" |
| F. Lin | “Skew tolerant high-speed digital phase detector” |
| Latency and Data path Control | |
| Authors | Patent Title |
| F. Lin | “System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal” |
| B. Keeth, B. Johnson and F. Lin | “Method and apparatus for setting and compensating read latency in a high speed DRAM” |
| B. Johnson, B. Keeth and F. Lin | “Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM” |
| F. Lin, B. Keeth, B. Johnson, SH. Lee | “Memory system and method for strobing data, command and address signals” |
| B. Keeth, B. Johnson, F. Lin | “Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM” |
| B. Johnson, F. Lin, B. Keeth | "Write latency tracking using a delay lock loop in a synchronous DRAM" |
| Others | |
| Authors | Patent Title |
| F. Lin, B. Johnson | “Method and apparatus for calibrating driver impedance” |
| F. Lin | “Circuits and methods of temperature compensation for refresh oscillator” |
| F. Lin | "Methods and apparatus for dividing a clock signal" |
| D. Pang, F. Lin, P. Silverstri | “Power supply voltage detection circuitry and methods for use of the same” |
| F. Lin | “Bias generator with feedback control” |
| SH. Lee, F. Lin | "Clock signal distribution with reduced parasitic loading effects" |
